1. Field of the Invention
The present invention generally relates to the field of fabrication of integrated circuits, and, more particularly, to the formation of an interconnection requiring the provision of a barrier layer between a bulk metal and a dielectric in which the interconnection is embedded.
2. Description of the Related Art
In an integrated circuit, a huge number of circuit elements, such as transistors, capacitors, resistors, and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of the integrated circuits, generally the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but requires one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal lines, providing for the inter-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, wherein the metal lines and vias may also be commonly referred to as interconnects.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the package density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide for the desired circuit functionality. Therefore, the number of stacked metallization layers increases as the number of circuit elements per chip area becomes larger. Since the fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of up to twelve stacked metallization layers that are required, for example, for sophisticated aluminum-based microprocessors, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum by a metal that allows higher current densities and hence allows reduction of the dimensions of the interconnections. For example, copper is a metal generally considered to be a viable candidate for replacing aluminum due to its superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum. In spite of these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures. In manufacturing metallization layers including copper, the so-called damascene technique is therefore preferably used wherein a dielectric layer is first applied and then patterned to receive trenches and vias, which are subsequently filled with copper. A further major drawback of copper is its property to readily diffuse in silicon dioxide, which is a well-established and approved dielectric material in fabricating integrated circuits.
It is therefore necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially avoid any out-diffusion of copper into the surrounding dielectric material, as copper may readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. The barrier material provided between the copper and the dielectric material should, however, in addition to the required barrier characteristics, exhibit good adhesion to the dielectric material as well as to the copper and should also have as low an electrical resistance as possible so as to not unduly compromise the electrical properties of the interconnection. It turns out, however, that a single material may not readily meet the requirements imposed on a desired barrier material. For example, a bi-layer comprised of tantalum and tantalum nitride are frequently used as barrier materials in combination with a copper damascene metallization layer. Tantalum, which effectively blocks copper atoms from diffusing into an adjacent material even when provided in extremely thin layers, however, exhibits only a poor adhesion to silicon dioxide based dielectrics, so that a copper interconnection including a tantalum barrier layer may suffer from reduced mechanical stability especially during the chemical mechanical polishing of the metallization layer, which is required for removing excess copper and planarizing the surface for the provision of a further metallization layer. The reduced mechanical stability during the CMP may, however, entail severe reliability concerns in view of reduced thermal and electrical conductivity of the interconnections. On the other hand, tantalum nitride exhibits excellent adhesion to silicon dioxide based dielectrics, but has very poor adhesion to copper. Consequently, in advanced integrated circuits having a copper-based metallization, typically a barrier bi-layer of tantalum nitride/tantalum is used, as will be described in more detail with reference to FIGS. 1a-1c. 
In FIG. 1a, a metallization structure 100 comprises a substrate 101, for example, a semiconductor substrate bearing a plurality of individual circuit elements (not shown), such as transistors, resistors, capacitors, and the like. The substrate 101 is to represent any type of appropriate substrate with or without any additional circuit elements and may, in particular, represent sophisticated integrated circuit substrates having included therein circuit elements with critical feature sizes in the deep submicron regime. A first dielectric layer 102 is formed above the substrate 101 and includes a metal interconnection 104 comprised of a metal line 103, such as a copper line, and a first barrier layer 106 comprised of tantalum, and a second barrier layer 105 comprised of tantalum nitride. The dielectric layer 102 and the metal interconnection 104 may represent a first metallization layer. A second dielectric layer 107 comprised of silicon dioxide or a silicon dioxide based dielectric material is formed over the first dielectric layer 102 and has formed therein a trench 109 and a via 108 connecting to the metal line 103. A first barrier layer 110 is formed on inner surfaces of the via 108 and the trench 109.
A typical process flow for forming the metallization structure 100 as shown in FIG. 1a may include the following steps, wherein, for the sake of simplicity, only the formation of the second metallization layer, i.e., of the second dielectric layer 107 and the metal interconnection to be formed therein, will be described in detail as the processes in forming the metal interconnection 104 in the first dielectric layer 102 may substantially involve the same process steps. Thus, after planarizing the dielectric layer 102, including the metal interconnection 104, the dielectric layer 107 is deposited by well-known deposition methods, such as plasma-enhanced CVD, wherein typically an etch stop layer (not shown) may be deposited prior to the formation of the second dielectric layer 107. Subsequently, the dielectric layer 107 is patterned by well-known photolithography and anisotropic etch techniques, wherein an intermediate etch stop layer (not shown) may be used in patterning the trench 109. It should be further noted that different approaches may be employed in forming the trench 109 and the via 108, such as a so-called via first, trench last approach, or a trench first, via last approach, wherein, in the former approach, the via 108 may be filled with metal prior to the formation of the trench 109. In the present example, a so-called dual damascene technique is described in which the trench 109 and the via 108 are simultaneously filled with metal. After the formation of the via 108 and the trench 109, the first barrier layer 110, comprised of tantalum nitride, is deposited by advanced physical vapor deposition (PVD) or ionized PVD (IPVD) techniques. Generally, the deposition of the thin barrier layer 110, typically with a thickness in the range of approximately 30-50 nm, in a reliable manner throughout the entire inner surfaces of the trench 109 and the via 108, wherein in particular the via 108 may have a large aspect ratio, requires advanced sputter tools that allow effective control of the directionality of the target atoms. An appropriate sputter tool will, in principle, be described later with reference to FIG. 3. Generally, it is desirable to select the deposition parameters so as to obtain a reliable coverage of the sidewalls and bottom surfaces of the trench 109 and the via 108 at a minimum thickness of the layer 110 so that only a minimum amount of space is “consumed” by the layer 110. Increasing the thickness of the barrier layer 110 would otherwise unduly compromise the electrical conductivity of the interconnection to be formed in the via 108 and the trench 109, especially when the feature sizes of the via 108 are scaled to 0.2 μm and less.
FIG. 1b schematically shows the metallization structure 100 with a second barrier layer 111 followed by a copper seed layer 112 formed on the structure 100 and within the trench 109 and the via 108. As previously noted, due to the superior adhesion characteristics of tantalum with regard to copper, the second barrier layer 111 is substantially comprised of tantalum so that in combination a desired high degree of adhesion is obtained to the surrounding dielectric material of the layer 107. The second barrier layer 111 may be deposited within the same sputter tool as the first barrier layer 110, wherein the supply of nitrogen is discontinued so as to substantially deposit tantalum instead of tantalum nitride. Thereafter, the copper seed layer 112 is deposited by sputter deposition, wherein a different deposition tool or a tool adapted to deposit tantalum and copper is used. The provision of the copper seed layer 112 may be advantageous in view of the crystallinity of the subsequently electrochemically deposited bulk copper compared to a direct provision of the copper on the tantalum barrier layer 111. Next, copper is deposited on the metallization structure 100, for example, by electroplating, in an amount to reliably fill the via 108 and the trench 109. Since reliable filling of the trench 109 requires a certain amount of “over-fill,” the excess copper has to be removed along with the first and second barrier layers 110, 111 so as to reliably insulate adjacent trenches 109 from each other. The removal of the excess material and the simultaneous planarization of the structure 100 is typically accomplished by CMP, wherein the superior overall adhesion characteristics of the combined first and second barrier layers 110, 111 allow the polishing of the structure 100 substantially without any issues regarding the mechanical stability of the inlaid copper in the trench 109 and the via 108.
FIG. 1c schematically shows the metallization structure 100 after completion of the above-described process sequence. Copper 113 is filled in the trench 109 and the via 108 and the excess metal of the barrier layers 110, 111 and of the copper 113 is removed to provide a substantially planar surface 115 for receiving a further metallization layer or a final passivation layer. Although the metallization structure 100 exhibits good adhesion characteristics while at the same time substantially preventing out-diffusion of copper into the surrounding dielectric layer 107, it is evident that at an interface 114 between the copper 103 and the copper 113 in the via 108, tantalum nitride of the layer 110 is directly in contact with the copper 103, thereby causing possible adhesion issues owing to the poor adhesion of tantalum nitride to copper. The reduced adhesion of the barrier layer 110 on the copper 103 may lead to a significantly increased transition resistance due to partial delamination or due to a void formation at the interface 114, thereby significantly negatively affecting the device's reliability and performance.
In view of the above-identified problems, there is a need for an improved barrier layer allowing the formation of more reliable metal interconnections, especially of copper interconnections.